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3977
PRELIMINARY INFORMATION
(Subject to change without notice) February 5, 2002 A3977SED
(PLCC)
LOAD SUPPLY1 SENSE1 SLEEP OUT1A ENABLE HOME GND GND 44 GND DIR 41 43 42 40 2 4 6 5 3 1 OUT1B
MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
The A3977SED and A3977SLP are complete microstepping motor drivers with built-in translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and 2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex P is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation.
Data Sheet 26184.22
VBB1 NC NC PFD RC1 7 39 NC CP2 CP1 VCP GND GND GND VREG STEP NC NC
8 9 10
CHARGE PUMP
38 37 36 35 34 33
PWM TIMER
GND 11 GND 12 GND 13 REF 14 /8
TRANSLATOR & CONTROL LOGIC
REG
32 31
RC2 15 LOGIC SUPPLY 16 NC 17 VBB2 VDD
30 29
18
MS1 20
21
GND 22
23
LOAD SUPPLY2 25
24
MS2 19
26
SENSE2
RESET 27
OUT2A
OUT2B 28
GND
GND
SR
Dwg. PP-075-1
ABSOLUTE MAXIMUM RATINGS at TA = +25C
Load Supply Voltage, VBB ............. 35 V Output Current, IOUT .................. 2.5 A* Logic Supply Voltage, VDD ........... 7.0 V Logic Input Voltage Range, VIN (tw >30 ns) .... -0.3 V to VDD + 0.3 V (tw <30 ns) .......... -1 V to VDD + 1 V Sense Voltage, VSENSE ................ 0.5 V Reference Voltage, VREF ................. VDD Package Power Dissipation, PD ................................ See page 3 Operating Temperature Range, TA ........................... -20C to +85C Junction Temperature, TJ ......... +150C Storage Temperature Range, TS ......................... -55C to +150C
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C.
Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3977 is supplied in a choice of two power packages, a 44lead plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28-lead TSSOP with an exposed thermal pad (suffix LP).
FEATURES
s s s s s s s s s 2.5 A, 35 V Output Rating Low rDS(on) Outputs, 0.45 Source, 0.36 Sink Typical Automatic Current Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current Decay Modes Home Output Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection
Always order by complete part number, e.g., A3977SLP .
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY VDD REF. SUPPLY REF UVLO AND FAULT 2V REGULATOR BANDGAP
VREG
CP2 CHARGE PUMP
CP1 VCP
LOAD SUPPLY
VBB1
DMOS H BRIDGE
DAC +-
SENSE1
VCP
RC1
PWM LATCH BLANKING MIXED DECAY
OUT1A OUT1B
4 STEP
PWM TIMER
MS1 MS2 HOME SLEEP VPFD SR
CONTROL LOGIC
GATE DRIVE
RESET
TRANSLATOR
DIR
SENSE1
DMOS H BRIDGE
VBB2
OUT2A OUT2B
ENABLE PWM TIMER PFD
PWM LATCH BLANKING MIXED DECAY
RC2 DAC
+
-
SENSE2
Dwg. FP-050-2
2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2002 Allegro MicroSystems, Inc.
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
A3977SLP
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
(TSSOP)
SENSE1 HOME DIR OUT1A PFD RC1 AGND REF RC2 LOGIC SUPPLY OUT2A MS2 MS1 SENSE2 1 2 3 4 VBB1 28 27 26 25 LOAD SUPPLY1 SLEEP ENABLE OUT1B CP2 CP1 VCP PGND VREG STEP OUT2B RESET SR LOAD SUPPLY2
Dwg. PP-075
5.0
SUFFIX 'LP', RJA = 28C/W*
4.0
SUFFIX 'ED', RJA = 32C/W
PWM TIMER
CHARGE PUMP
5 6 7 8 9 10 11 12 13 14
24 23 22 21
3.0
TRANSLATOR & CONTROL LOGIC
2.0
/8
REG
20 19 18 17 16
VDD
1.0
SUFFIX 'LP', RJA = 55C/W
0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150
VBB2
15
Dwg. GP-018-2
Package Thermal Resistance, RJA A3977SLP ........................ 28C/W* A3977SED ........................ 32C/W A3977SLP ........................ 55C/W
* Measured on JEDEC standard "High-K" four-layer board. Measured on typical two-sided PCB with three square inches (1935 mm2) copper ground area.
Table 1. Microstep Resolution Truth Table MS1 L H L H MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Output Drivers Load Supply Voltage Range VBB Operating During sleep mode Output Leakage Current IDSS VOUT = VBB VOUT = 0 V Output On Resistance rDS(on) Source driver, IOUT = -2.5 A Sink driver, IOUT = 2.5 A Body Diode Forward Voltage VF Source diode, IF = -2.5 A Sink diode, IF = 2.5 A Motor Supply Current IBB fPWM < 50 kHz Operating, outputs disabled Sleep mode Control Logic Logic Supply Voltage Range Logic Input Voltage VDD VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) Maximum STEP Frequency HOME Output Voltage fSTEP VOH VOL Blank Time Fixed Off Time tBLANK toff IOH = -200 A IOL = 200 A Rt = 56 k, Ct = 680 pF Rt = 56 k, Ct = 680 pF VIN = 0.7VDD VIN = 0.3VDD Operating 3.0 0.7VDD - -20 -20 500* 0.7VDD - 700 30 5.0 - - <1.0 <1.0 - - - 950 38 5.5 - 0.3VDD 20 20 - - 0.3VDD 1200 46 V V V A A kHz V V ns s 8.0 0 - - - - - - - - - - - <1.0 <1.0 0.45 0.36 - - - - - 35 35 20 -20 0.57 0.43 1.4 1.4 8.0 6.0 20 V V A A V V mA mA A Symbol Test Conditions Min. Typ. Max. Units
continued next page ...
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Control Logic (cont'd) Mixed Decay Trip Point PFDH PFDL Ref. Input Voltage Range Reference Input Current Gain (Gm) Error (note 3) VREF IREF EG VREF = 2 V, Step = 3 VREF = 2 V, Step = 5 VREF = 2 V, Step = 9 Crossover Dead Time Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current tDT TJ TJ VUVLO VUVLO IDD fPWM < 50 kHz Outputs off Sleep mode Increasing VDD SR enabled Operating - - 0 - - - - 100 - - 2.45 0.05 - - - 0.6VDD 0.21VDD - 0 - - - 475 165 15 2.7 0.10 - - - - - VDD 3.0 10 5.0 5.0 800 - - 2.95 - 12 10 20 V V V A % % % ns C C V V mA mA A Symbol Test Conditions Min. Typ. Max. Units
* Operation at a step frequency greater than the specified minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] - VSENSE)/(VREF/8)
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Functional Description
Device Operation. The A3977 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarterand eighth-step modes. The current in each of the two output H-bridges, all n-channel DMOS, is regulated with fixed off time pulse-width modulated (PWM) control circuitry. The H-bridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DAC's output voltage controlled by the output of the translator. At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that H-bridge will be set by the PFD input (fast, slow or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that H-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET). The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the RESET input goes high. Home Output (HOME). The HOME output is a logic output indicator of the initial state of the translator. At power up the translator is reset to the home state (see figures for home state conditions). Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). Microstep Select (MS1 and MS2). Input terminals MS1 and MS2 select the microstepping format per Table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR). The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control. Each H-bridge is controlled by a fixed off time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RS. When the voltage across the current sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see Table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax It is critical to ensure that the maximum rating (0.5 V) on the SENSE terminal is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 x VREF/8. In all other modes VREF should not exceed 4 V.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Functional Description (cont'd)
Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 k to 100 k is approximated by: toff = RTCT RC Blanking. In addition to the fixed off time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 F ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 F capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE). This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on VCP) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 F capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6VDD and 0.21VDD, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: tFD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD, the device will switch to slow-decay mode for the remainder of the fixed off-time period.
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Functional Description (cont'd)
Synchronous Rectification. When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. The synchronous rectification can be set in either active mode or disabled mode. Active mode. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. Disabled mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes.
Timing Requirements (TA = +25C, VDD = 5 V, Logic Levels are VDD and Ground)
STEP
50%
C A B
D
MS1/MS2/ DIR/RESET
E
SLEEP
Dwg. WP-042
A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 s D. Minimum STEP Low Time ......................... 1.0 s E. Maximum Wake-Up Time ......................... 1.0 ms
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Applications Information
Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 F is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 - 13, 22 - 24, and 33 - 35). On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be connected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor's traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Table 2. Step Sequencing (DIR = L) Phase 2 Current [%Itripmax] 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -98.08 -100.00 -98.08 -92.39 -83.15 -70.71 -55.56 -38.27 -19.51 0.00 Phase 1 Current [%Itripmax] 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -98.08 -100.00 -98.08 -92.39 -83.15 -70.71 -55.56 -38.27 -19.51 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 100.00
Full Step #
Half Step # 1
Quarter Step # 1 2
Eighth Step # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Step Angle 0 11.25 22.50 33.75 45* 56.25 67.50 78.75 90 101.25 112.50 123.75 135 146.25 157.50 168.75 180 191.25 202.50 213.75 225 236.25 247.50 258.75 270 281.25 292.50 303.75 315 326.25 337.50 348.75 360
1
2
3 4
3
5 6
2
4
7 8
5
9 10
3
6
11 12
7
13 14
4
8
15 16
9 * Home state; HOME output low.
17
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Full Step Operation MS1 = MS2 = L, DIR = H
STEP INPUT
HOME OUTPUT
SLOW DECAY
70.7%
PHASE 1 CURRENT
-70.7%
SLOW DECAY
70.7%
PHASE 2 CURRENT
-70.7%
Dwg. WK-004-15
The vector addition of the output currents at any step is 100%.
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Half Step Operation MS1 = H, MS2 = L, DIR = H
STEP INPUT
HOME OUTPUT
MIXED DECAY SLOW DECAY SLOW DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY
100% 70.7%
PHASE 1 CURRENT
-70.7% -100%
SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY
100% 70.7%
PHASE 2 CURRENT
70.7% -100%
Dwg. WK-004-14
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Quarter Step Operation MS1 = L, MS2 = H, DIR = H
STEP INPUT
HOME OUTPUT
SLOW DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
100% 70.7% 38.3%
PHASE 1 CURRENT
-38.3% -70.7% -100%
MIXED DECAY
SLOW DECAY
MIXED DECAY
SLOW DECAY
100% 70.7% 38.3%
PHASE 2 CURRENT
-38.3% -70.7% -100%
Dwg. WK-004-13
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
8 Microstep/Step Operation MS1 = MS2 = H, DIR = H
STEP INPUT
HOME OUTPUT
SLOW DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
100% 70.7% 38.3%
PHASE 1 CURRENT
-38.3% -70.7% -100%
MIXED DECAY
SLOW DECAY
MIXED DECAY
SLOW DECAY
100% 70.7% 38.3%
PHASE 2 CURRENT
-38.3% -70.7% -100%
Dwg. WK-004-12
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
Terminal List Terminal Name GND SENSE1 HOME DIR OUT1A NC PFD RC1 GND AGND REF RC2 LOGIC SUPPLY NC OUT2A MS2 MS1 SENSE2 GND LOAD SUPPLY2 SR RESET OUT2B NC STEP VREG PGND GND VCP CP1 CP2 NC OUT1B ENABLE SLEEP LOAD SUPPLY1 A3977SLP ( TSSOP) - 1 2 3 4 - 5 6 - 7* 8 9 10 - 11 12 13 14 - 15 16 17 18 - 19 20 21* - 22 23 24 - 25 26 27 28 A3977SED (PLCC) 44, 1, 2 3 4 5 6 7, 8 9 10 11, 12, 13 - 14 15 16 17 18 19 20 21 22, 23, 24 25 26 27 28 29, 30 31 32 - 33, 34, 35 36 37 38 39 40 41 42 43
Terminal Description Analog and power ground Sense resistor for bridge 1 Logic output Logic Input DMOS H bridge 1 output A No (internal) connection Mixed decay setting Analog Input for fixed offtime - bridge 1 Analog and power ground Analog ground Gm reference input Analog input for fixed offtime - bridge 2 VDD, the logic supply voltage No (internal) connection DMOS H bridge 2 output A Logic input Logic input Sense resistor for bridge 2 Analog and power ground VBB2, the load supply for bridge 2 Logic input Logic input DMOS H bridge 2 output B No (internal) connection Logic input Regulator decoupling Power ground Analog and power ground Reservoir capacitor Charge pump capacitor Charge pump capacitor No (internal) connection DMOS H bridge 1 output B Logic input Logic input VBB1, the load supply for bridge 1
* AGND and PGND on the TSSOP package must be connected together externally.
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
A3977SED
28 18
29 0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050
BSC INDEX AREA
17
0.032 0.026
Dimensions in Inches (controlling dimensions)
39
7
40 0.020
MIN
44
1
2
6
0.656 0.650 0.695 0.685
Dwg. MA-005-44A in
0.180 0.165
28
18
29 8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510
INDEX AREA
17
0.812 0.661
Dimensions in Millimeters (for reference only)
8.10 7.39 1.27
BSC
39
7
40 0.51
MIN
44 16.662 16.510
1
2
6
4.57 4.20
17.65 17.40
Dwg. MA-005-44A mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece. Supplied in standard sticks/tubes of 27 devices or add "TR" to part number for tape and reel.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
A3977SLP
0.130 28
MIN
15
0.0394
REF
0.177 0.169
INDEX AREA
0.0591
MIN GAUGE PLANE SEATING PLANE
0.0098
BSC
0.012 0.0075
1
2
3 0.386 0.378
0.026
BSC
0 TO 8
0.030 0.018
Dimensions in Inches (for reference only)
0.260 0.244 0.0472
MAX
0.0079 0.0035 0.0059 0.00
EXPOSED THERMAL PAD
Dwg. MA-008-30 in
3.30 28
MIN
15
1.00
REF
4.50 4.30
INDEX AREA
1.50
MIN GAUGE PLANE SEATING PLANE
0.25
BSC
0.30 0.19
1
2
3 9.80 9.60
0.65
BSC
0 TO 8
0.75 0.45
Dimensions in Millimeters (controlling dimensions)
6.60 6.20
1.20
MAX
0.20 0.09 0.15 0.00
EXPOSED THERMAL PAD
Dwg. MA-008-30 mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Supplied in standard sticks/tubes of 49 devices or add "TR" to part number for tape and reel. Dimensions meet JEDEC MO-153AET. However, thermal pad for A3977SLP is approximately 3.0 mm x 5.0 mm (0.12" x 0.20").
www.allegromicro.com
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
MOTOR DRIVERS
Output Ratings* Part Number INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS 3-Phase Power MOSFET Controller -- 28 V 3933 3-Phase Power MOSFET Controller -- 50 V 3932 3-Phase Back-EMF Controller/Driver 900 mA 14 V 8902-A 3-Phase Controller/Driver 2.0 A 45 V 2936-120 INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS Dual Full Bridge with Protection & Diagnostics 500 mA 30 V 3976 PWM Current-Controlled Dual Full Bridge 650 mA 30 V 3966 PWM Current-Controlled Dual Full Bridge 650 mA 30 V 3968 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 2916 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 2919 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 6219 PWM Current-Controlled Dual Full Bridge 800 mA 33 V 3964 PWM Current-Controlled Dual DMOS Full Bridge 1.0 A 35 V 3973 PWM Current-Controlled Full Bridge 1.3 A 50 V 3953 PWM Current-Controlled Dual Full Bridge 1.5 A 45 V 2917 PWM Current-Controlled DMOS Full Bridge 1.5 A 50 V 3948 PWM Current-Controlled Microstepping Full Bridge 1.5 A 50 V 3955 PWM Current-Controlled Microstepping Full Bridge 1.5 A 50 V 3957 PWM Current-Controlled Dual DMOS Full Bridge 1.5 A 50 V 3972 PWM Current-Controlled Dual DMOS Full Bridge 1.5 A 50 V 3974 Dual Full-Bridge 2.0 A 50 V 2998 PWM Full-Bridge 2.0 A 50 V 3951 PWM Current-Controlled Full Bridge 2.0 A 50 V 3952 PWM Current-Controlled DMOS Full Bridge 2.0 A 50 V 3958 Dual DMOS Full Bridge 2.5 A 50 V 3971 PWM Current-Controlled DMOS Full Bridge 3.0 A 50 V 3959 UNIPOLAR STEPPER MOTOR & OTHER DRIVERS Unipolar Stepper-Motor Quad Drivers 1.0 A 46 V 7024 & 7029 Unipolar Microstepper-Motor Quad Driver 1.2 A 46 V 7042 Unipolar Stepper-Motor Translator/Driver 1.25 A 50 V 5804 Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2540 Unipolar Stepper-Motor Quad Driver 3.0 A 46 V 7026 Unipolar Microstepper-Motor Quad Driver 3.0 A 46 V 7044 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors. Function
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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